1. Field of the Invention
This invention relates to a process for forming interconnections between conductive layers in an integrated circuit and, more particularly, relates to the process for forming conductive interconnections between separate conductive layers in an integrated circuit without having to open up and fill vias.
2. Discussion of Background and Prior Art
As the densities of integrated circuits increase, it has become necessary to use two or more conductive layers in an integrated circuit in order to make all the electrical interconnections required between the electrically active regions. The conductive layers may be a metal such as tungsten, aluminum, silicides, doped polycrystalline silicon or a composite material such as aluminum-copper-silicon. These conductive layers have necessarily been separated by insulating layers in order to prevent shorting. At times, in accordance with patterns of electrical interconnection it is necessary to interconnect these spaced apart, overlying conductive layers. The heights of the interconnections or pedestals would vary from about 0.8 .mu.m to 3.0 .mu.m with taller pedestals being employed for higher current densities and higher level interconnections.
The conventional approach to forming interconnections has been to pattern the intervening insulating layer in order to identify regions where interconnections are desired. These regions are then opened up by means such as chemical or dry etching. The openings, called vias, are then filled with a conductive material which physically bridges the gap between the underlying and the overlying conductive layer and makes electrical contact between them. Such processes require numerous masks and process steps and do not necessarily produce self-aligned structures. In an attempt to simplify the techniques for forming interconnections between conductive layers, it has been proposed to first form pedestals in the underlying layer on which the overlying layer rests, and thereafter apply an insulating layer and then an overlying conductive layer. For example, in J. R. Kitcher, "Integral Stud for Multilevel Metal", IBM Technical Disclosure Bulletin, v. 23, No. 4, p. 1395, September 1980, a layer of stud metal is patterned by photoresist on a magnesium oxide mask. Metal studs are then formed by reactive ion etching, followed by application of an insulating layer, planarization to expose the tips of the studs and finally the application of a second conductive layer which contacts the tips of the studs. For this process a separate masking step is required to expose the studs and dimensional allowance must be made for any misalignment of the pedestals with respect to the first conductive layer.
Self-alignment is a preferred condition when overlying layers are fabricated. When the structural features on a given layer are in self-alignment with overlying or underlying layers, the size of the features may be reduced since it is not necessary to oversize the features to compensate for margins of error in alignment. Thus, more devices may be fabricated per unit area. The desirability of self-aligned processes and the various techniques for achieving self-alignment are known in the semiconductor processing art. See, e.g., I. E. Magdo et al., "Self-Aligned ROI to SAM Structure", IBM Technical Disclosure Bulletin, v. 24, no. 10, pp. 5115-5118, March 1982; and P. W. Betz et al., "Self-Aligned Contact Holes", IBM Technical Disclosure Bulletin, v. 24, no. 9, pp. 4643-4644, February 1982.
Selective etching is a useful process technique in the semiconductor industry. By selective etching is meant an etch which etches one material preferentially to another material. By the use of this technique, it is possible to enhance structural complexity without having to utilize additional masking steps. This is desirable because separate masks and the associated processing steps reduce yield and add to the cost of processing. Selective etching has been used, for example, in conjunction with reactive ion etch equipment. See, e.g., H. W. Lehmann et al., "Dry Etching for Pattern Transfer", J. Vacuum Science and Technology, v. 17, No. 5, September/October 1980, pp. 1177. Various etches which have selective etching properties with respect to the several semiconductor materials, e.g., silicon nitride, silicon dioxide, silicon, aluminum alloys, etc., are known in the art. See D. N. K. Wang et al., "Reactive-ion etching eases restrictions on materials and feature sizes", Electronics, Nov. 3, 1983, p. 157; and L. M. Ephrath, "Reactive Ion Etching for VLSI", IEEE Transactions on Electron Devices, v. ED-28, no. 11, November 1981, p. 1315.
It is therefore an object of the present invention to provide conductive interconnections between conductive layers without having to form openings in intervening insulating layers.
It is another object of the present invention to construct pedestals on an underlying conductive layer which extend up through an insulating layer to contact an overlying conductive layer.
It is another object of the present invention to provide a fabrication process for interconnecting different levels of metallization whereby selective etching is used in lieu of a mask and etch process.